ATA8743-PXQW【PDF 185/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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185

9152BINDCO02/10

ATA8743

28.6.1

Serial Programming Algorithm

When writing serial data to the ATtiny24/44/84, data is clocked on the rising edge of SCK.

When reading data from the ATtiny24/44/84, data is clocked on the falling edge of SCK. See

Figure 29-3 and Figure 29-4 for timing details.

To program and verify the ATtiny24/44/84 in the Serial Programming mode, the following

sequence is recommended (see four byte instruction formats in Table 28-11):

1. Power-up sequence:

Apply power between V

and GND while RESET

and SCK are set to 0. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET

must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to 0.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of synchro-

nization. When in sync. the second byte (0x53), will echo back when issuing the third

byte of the Programming Enable instruction. Whether the echo is correct or not, all four

bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET

positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one byte at a

time by supplying the 5 LSB of the address and data together with the Load Program

memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program memory

Page is stored by loading the Write Program memory Page instruction with the 3 MSB of

the address. If polling (RDY/BSY)

is not used, the user must wait at least t

WD_FLASH

before

issuing the next page. (See Table 28-10 on page 186.) Accessing the serial program-

ming interface before the Flash write operation completes can result in incorrect

programming.

5. A: The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is first

automatically erased before new data is written. If polling (RDY/BSY)

is not used, the

user must wait at least t

WD_EEPROM

before issuing the next byte. (See Table 28-10 on

page 186.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed.

B: The EEPROM array is programmed one page at a time. The Memory page is loaded

one byte at a time by supplying the 2 LSB of the address and data together with the Load

EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading

the Write EEPROM Memory Page Instruction with the 4 MSB of the address. When using

EEPROM page access only byte locations loaded with the Load EEPROM Memory Page

instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY)

not used, the used must wait at least t

WD_EEPROM

before issuing the next page (See Table

28-10 on page 186). In a chip erased device, no 0xFF in the data file(s) need to be

programmed.

6. Any memory location can be verified by using the Read instruction which returns the con-

tent at the selected address at serial output MISO.

7. At the end of the programming session, RESET

can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET

to 1.

Turn V

power off.

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